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74LVT16543 * 74LVTH16543 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs
January 2000 Revised October 2001
74LVT16543 * 74LVTH16543 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs
General Description
The LVT16543 and LVTH16543 16-bit transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. Each byte has separate control inputs, which can be shorted together for full 16-bit operation. The LVTH16543 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These transceivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16543 and LVTH16543 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation.
Features
s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH16543) s Also available without bushold feature (74LVT16543) s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink -32 mA/+64 mA s Functionally compatible with the 74 series 16543 s Latch-up conforms to JEDEC JED78 s ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V
Ordering Code:
Order Number 74LVT16543MEA (Preliminary) 74LVT16543MTD (Preliminary) 74LVTH16543MEA 74LVTH16543MTD Package Number MS56A MTD56 MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
(c) 2001 Fairchild Semiconductor Corporation
DS012449
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74LVT16543 * 74LVTH16543
Connection Diagram
Pin Descriptions
Pin Names OEABn OEBAn CEABn CEBAn LEABn LEBAn A0-A15 Description
A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Enable Input (Active LOW) B-to-A Enable Input (Active LOW) A-to-B Latch Enable Input (Active LOW) B-to-A Latch Enable Input (Active LOW) A-to-B Data Inputs or B-to-A 3-STATE Outputs
B0-B15
B-to-A Data Inputs or A-to-B 3-STATE Outputs
Functional Description
The LVT16543 and LVTH16543 contain two sets of D-type latches, with separate input and output controls for each. For data flow from A to B, for example, the A to B Enable (CEAB) input must be LOW in order to enter data from the A Port or take data from the B Port as indicated in the Data I/ O Control Table. With CEAB LOW, a low signal on (LEAB) input makes the A to B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB line puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the B output buffers are active and reflect the data present on the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA. Each byte has separate control inputs, allowing the device to be used as two 8-bit transceivers or as one 16-bit transceiver.
Data I/O Control Table
Inputs CEABn H X L X L LEABn X H L X X OEABn X X X H L Latched Latched Transparent -- -- Latch Status (Byte n) Output Buffers (Byte n) High Z -- -- High Z Driving
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown; B-to-A flow control is the same, except using CEBAn, LEBAn and OEBAn
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74LVT16543 * 74LVTH16543
Logic Diagrams
Byte 1 (0:7)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LVT16543 * 74LVTH16543
Absolute Maximum Ratings(Note 1)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 2) VI < GND VO < GND VO > VCC VO > VCC Output at HIGH State Output at LOW State V V mA mA mA mA mA
-0.5 to +4.6 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -50 -50
64 128
64 128 -65 to +150
C
Recommended Operating Conditions
Symbol VCC VI IOH IOL TA Supply Voltage Input Voltage HIGH-Level Output Current LOW-Level Output Current Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V-2.0V, VCC = 3.0V Parameter Min 2.7 0 Max 3.6 5.5 Units V V mA
-32
64
-40
0
85 10
C
ns/V
t/V
Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 2: IO Absolute Maximum Rating must be observed.
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74LVT16543 * 74LVTH16543
DC Electrical Characteristics
Symbol VIK VIH VIL VOH Parameter Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VCC (V) 2.7 2.7-3.6 2.7-3.6 2.7-3.6 2.7 3.0 VOL Output LOW Voltage 2.7 2.7 3.0 3.0 3.0 II(HOLD) (Note 3) II(OD) (Note 3) II Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF IPU/PD Power Off Leakage Current Power Up/Down 3-STATE Output Current IOZL (Note 3) 3-STATE Output Leakage Current IOZL IOZH IOZH+ ICCH ICCL ICCZ ICCZ+ ICC 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current Power Supply Current Power Supply Current Power Supply Current Power Supply Current Increase in Power Supply Current (Note 6)
Note 3: Applies to bushold versions only (74LVTH16543) Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
T A = -40C to +85C Min 2.0 0.8 VCC - 0.2 2.4 2.0 0.2 0.5 0.4 0.5 0.55 75 -75 500 -500 10 1 -5 1 100 100 -5 -5 5 5 10 0.19 5 0.19 0.19 Max -1.2
Units V V V V V V V V V V A A A A A A A A A A A A A A A mA mA mA mA
Conditions II = -18 mA VO 0.1V or VO VCC - 0.1V IOH = -100 A IOH = -8 mA IOH = -32 mA IOL = 100 A IOL = 24 mA IOL = 16 mA IOL = 32 mA IOL = 64 mA VI = 0.8V VI = 2.0V (Note 4) (Note 5) VI = 5.5V VI = 0V or VCC VI = 0V VI = VCC 0V VI or VO 5.5V VO = 0.5V to 3.0V VI = GND or VCC VO = 0.0V VO = 0.5V VO = 3.6V VO = 3.0V VCC < V O 5.5V Outputs HIGH Outputs LOW Outputs Disabled VCC V O 5.5V, Outputs Disabled One Input at VCC - 0.6V Other Inputs at VCC or GND
Bushold Input Minimum Drive
3.0 3.0 3.6 3.6 3.6 0 0-1.5V 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6
IOZH (Note 3) 3-STATE Output Leakage Current
3.6
0.2
mA
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) 3.3 3.3
(Note 7)
TA = 25C Units Max V V Conditions CL = 50 pF, RL = 500 (Note 8) (Note 8)
Min
Typ 0.8 -0.8
Note 7: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 8: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. Output under test held LOW.
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74LVT16543 * 74LVTH16543
AC Electrical Characteristics
TA = -40C to +85C Symbol Parameter CL = 50 pF, RL = 500 VCC = 3.3 0.3V Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ tW tS Propagation Delay Data to Outputs Propagation Delay LE to A or B Output Enable Time OE to A or B Output Disable Time OE to A or B Output Enable Time CE to A or B Output Disable Time CE to A or B Pulse Duration Setup Time LE LOW A or B before LE, Data HIGH A or B before LE, Data LOW A or B before CE, Data HIGH A or B before CE, Data LOW tH Hold Time A or B after LE, Data HIGH A or B after LE, Data LOW A or B after CE, Data HIGH A or B after CE, Data LOW tOSLH tOSHL Output to Output Skew (Note 9) 1.2 1.2 1.3 1.3 1.3 1.3 2.0 2.0 1.3 1.3 2.0 2.0 3.3 0.5 0.8 0.5 0.6 1.5 1.2 1.7 1.6 1.0 1.0 Max 4.2 4.4 4.7 5.1 4.7 5.1 5.5 4.9 4.6 5.0 5.5 4.9 VCC = 2.7V Min 1.2 1.2 1.3 1.3 1.3 1.3 2.0 2.0 1.3 1.3 2.0 2.0 3.3 0.5 1.3 ns 0.0 1.1 0.7 1.3 ns 0.9 1.8 1.0 1.0 ns Max 4.5 4.9 5.5 5.8 5.4 6.1 5.7 4.9 5.6 6.1 5.8 4.9 ns ns ns ns ns ns ns Units
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 10)
Symbol CIN CI/O Parameter Input Capacitance Input/Output Capacitance Conditions VCC = OPEN, VI = 0V or VCC VCC = 3.0V, VO = 0V or VCC Typical 4 8 Units pF pF
Note 10: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
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74LVT16543 * 74LVTH16543
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS56A
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74LVT16543 * 74LVTH16543 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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